clock - Vhdl with no clk -

I have a clock in my vhdl code but I do not use it, just my process depends on hand shake When one component is over and out, this output is in the sensitivity list of my FSM and then becomes an input for the next component and of course its output is in the sensitivity list of my FSM (such address When to End the Component Will count) ... and so on. Is this method wrong? It works in simulation and also works in post-simulation simulations, but I get such warnings: Warning: I prevent high violation in relation to CLK; And the warning: I hold low contradiction with respect to the CLK;

Is this warning not important or will my code harm my FPG because it is not dependent on one watch?

The warning you are getting is a violation of time. You get them because the tools find that your design does not comply with the time restrictions required for internal primitives.

For example, look-tables (which is one of the main building blocks inside an FPGA) need to be held for a specific time to freeze the input. It is very difficult to make sure that your whole time only depends on the components and components of the delay, and completely switches on asynchronous basis.

Your actual design (based on most size and complexity)), I guess you will end up with a very hard-to-debug errors, when you get it inside an FPGA will do. You will get a lot of, very easy time, using a clock, it gives you an indication of when the signal arrives, and it will allow you to use the internal equipment to check your time. You also find it easier to interface for other devices, and your system will be less sensitive for noise inputs.

So, in all, use a clock. You (probably) do not harm your FPG by doing this, but one watch will save you from many troubles.