linux - How does ARM switch to svc mode in IRQ handler? -

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The following code snippet is derived from Linux v2.6.11. Something similar exists in v3.8 as well. 

  mrs r13, cpsr bic r13, r13, #MODE_MASK orr r13, r13, #MODE_SVC MSR spsr_cxsf, r13 @ Switch SVC_32 mode and LR, LR, # 15 LDR LR, [PC, LR , Lsl # 2] movs pc, lr @ change mode and branches   
 See the following link for the actual file:  
 I think that mode bits write in CPSR Current ARM mode can change. But how to write in SSPR (instead of CPSR), as a result of switching to SVC_32 mode?  
 (Or) Something is happening in the previous instructions "Ammos PC, LR". Can anyone help me understand this?   
 
 
 a  mov  or  sub  
 It copies the contents of the SPSR into the CPSR and enters the value of the source register. Program Counter (In this case, Link Register).  
 In your example, this effectively sets the SVC mode mode and returns the function to the one time.  
 There is more information about this on this.

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